This application claims the priority of Korean Patent Application No. 2003-59487, filed on Aug. 27, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a power module package formed of a power semiconductor device and other related devices, and more particularly, to a power module flip chip package in which the power semiconductor device is packaged using a flip chip method.
2. Description of the Related Art
Power module packages that are widely used at present use wire bonding which is a source of high resistance and noise. Recently, as power modules have been highly efficient, the number of connections using wire bonding has increased by ten to thirty times. However, the added number of bond wires has increased the resistance, signal delay, and signal interference and that has limited the further efficiency and density of future power modules.
In addition, it is difficult to apply the power module packages which use wire bonding to various combinations of a power semiconductor device and additional devices (e.g., control circuit device, protection circuit device, etc.) that have a variety of applications.
A power module package that reduces the resistance and inductance caused by the wired bonding is disclosed in the U.S. Pat. No. 6,442,033. The power module package disclosed in the above patent is formed of a power semiconductor device placed between two package substrates.
However, since the power semiconductor device is placed between the two package substrates, the power module package is limited to package substrates that have similar Young's Modulus and coefficients of thermal expansion. The packaging process is also very complicated.